The Hong Kong Polytechnic University (PolyU) has announced a breakthrough in transistor technology that could redefine the future of integrated circuits. A research team led by Prof. Jianhua HAO, Head of the Department of Physics and Materials and Chair Professor of Materials Physics and Devices at PolyU, has engineered a novel tunnelling field-effect transistor (TFET) using two-dimensional (2D) nanomaterials. This development overcomes the physical 'Boltzmann limit' that has constrained traditional semiconductor technology, offering new possibilities for energy-efficient computing and next-generation AI chips.
The Boltzmann limit refers to the minimum voltage required to switch a transistor on and off, which is 60 millivolts (mV) at room temperature. Conventional transistors rely on thermionic emission, where electrons are thermally excited over a barrier. This process demands a certain voltage, making it impossible to achieve subthreshold swing (SS) values below 60 mV per decade. This limit has become a significant barrier to improving energy efficiency and performance in microelectronics.
Prof. Hao's team, collaborating with the National University of Singapore, The Hong Kong University of Science and Technology, Peking University, and the Singapore University of Technology and Design, has demonstrated a TFET that utilizes quantum tunnelling. This mechanism allows electrons to pass through a barrier rather than over it, breaking the Boltzmann limit. The research was published in the prestigious journal Science.
The team created an ultra-thin heterostructure of alternating 2D bismuth and indium selenide layers using pulsed laser deposition. By precisely controlling the layer structure, they transformed the normally semi-metallic bismuth into a semiconductor in its 2D form. This enables charge carriers to tunnel efficiently into indium selenide, achieving SS values well below the 60 mV per decade limit.
The device operates at room temperature on silicon substrates and requires a gate-voltage range of only 160 mV, compared to the typical 800 mV. This significant reduction in voltage leads to lower power consumption and heat generation, which is crucial for high-performance computing. Additionally, the TFET delivers a high output current alongside an exceptionally high ON/OFF current ratio, addressing a common challenge in experimental TFETs. This performance allows it to drive multiple downstream logic gates and diminish circuit delay, making it suitable for practical applications.
The implications of this breakthrough are profound. As the demand for AI and advanced semiconductor applications grows, the need for ultra-low-power, high-performance integrated circuits becomes critical. This TFET technology could enable more energy-efficient devices, from smartphones to data centers, and accelerate the development of next-generation AI chips. Prof. Hao emphasized, 'By adopting quantum tunnelling, our TFET breaks through this boundary, paving the way for ultra-low-power, high-performance integrated circuits essential for emerging AI chips and advanced semiconductor applications.'
The research team's success in creating a TFET that operates efficiently at room temperature on silicon substrates marks a significant step toward commercial viability. The use of 2D materials and pulsed laser deposition is compatible with existing semiconductor manufacturing processes, potentially facilitating integration into current chip production.
This achievement not only demonstrates a fundamental scientific advance but also offers a practical solution to the energy efficiency challenges facing the semiconductor industry. As the world moves toward more connected and intelligent systems, such innovations will be pivotal in shaping the future of technology.
